Job Title:          Director of Layout

Job Duties:     The Layout Director will be responsible for all aspects of chip physical design from layout through tape-out. The Layout Director will be responsible to scale the physical design organization from early stage start up to revenue generating growth stage.  The ideal candidate is a self-starter, key team member leading small fast moving teams, and is a highly motivated engineer with excellent technical, managerial, and communications skills. The managerial role in a start up requires individual contributions with the opportunity to grow the organization and physical design processes. The position will have significant exposure with opportunity for career growth.

Responsibilities:

  • Lead physical design team in development of complex power management chips
  • Manage and actively participate in layout of individual circuits and large, complex chip hierarchies including top-level floor-planning and power routing.
  • Responsible for chip finishing: fill metal density, physical verification (DRC, ERC, LVS)
  • Manage layout employees and contractors, train/supervise/implement best practices
  • Work with engineering teams to define and manage schedules & resources, and negotiate necessary layout trade-offs
  • Improve tool flow and enhance layout productivity

Key Qualifications:

  • Proven track record of physical design and producing (in high volume) profitable complex analog mixed signal chips and/or RF chips in deep submicron process at and below 28nm
  • Chip floor and block level planning in high power, high frequency, high switching-noise environments.
  • Drawing of complex layouts of CMOS RF and Analog Mixed signal cells and blocks
  • Solid understanding of physical, electrical, and DFM rules for deep-submicron CMOS processes
  • Knowledge of semiconductor devices and fabrication principles including; matching, electromigration, RF delay, parasitic coupling, signal balancing
  • Knowledge of nanometer issues such as Well-Proximity Effect (WPE), Shallow Trench Isolation (STI),multiple patterning, and pattern density management
  • Proficiency with industry-standard layout and verification tool; Cadence: Virtuoso IC6.1, Assura, PVS; Mentor: Calibre
  • Recruiting, building, and leading teams
  • 10+ years industry experience, either with a fabless semiconductor company or with a tier one integrated analog IC company in custom analog IC circuit design, including design of amplifiers, comparators, references, bias circuits, switched capacitor or sampling circuits, high performance A/D and D/A, linear regulators, DC-DC switching converters, power management
  • 3+ years experience in a similar management role
  • Excellent written and verbal communications skills
  • Educational: MSEE, MSCS, or equivalent experience

Job Site:            R2 Semiconductor, Inc., 1196 Borregas Avenue, Suite 201, Sunnyvale, CA 94089

Hours:               Full-time (40 hours per week)

Contact:            Send resume HR, R2 Semiconductor, Inc., 1196 Borregas Avenue, Suite 201, Sunnyvale, CA 94089