Job Title: Analog Layout Designer
Job Duties: The Analog Layout Designer will be responsible for all aspects of physical chip design from layout through tape-out. The candidate should have experience and a proven track record supporting full-custom analog, Power Management IC’s and/or Analog/RF at 28nm and below. The ideal candidate is a self-starter, key team member leading small fast moving teams, and is a highly motivated engineer with excellent technical, managerial, and communications skills. The position will have significant exposure with opportunity for career growth. As a member of the Analog Mixed-Signal design and layout team, you will be working on the latest technology nodes to create world-class analog macros. This is a fast-paced work environment with endless learning opportunities.
Requirements: 10+ years industry experience in analog mixed-signal layout design of deep submicron CMOS circuits, including design of amplifiers, comparators, references, bias circuits, switched capacitor or sampling circuits, high performance A/D and D/A, linear regulators, DC-DC switching converters, power management.
- Self starter, highly motivated, results driven, and passionate about winning
- Proven track record of physical design and producing (in high volume) profitable complex analog mixed signal chips
- Proven track record for the following:
- Full custom analog and/or RF in deep submicron process below 28nm
- Chip top- and block-level floorplanning in high power, high frequency, high switching-noise environments.
- Drawing complex layouts of CMOS RF and Analog Mixed-Signal cells and blocks
- Solid understanding of physical, electrical, and DFM rules for deep-submicron CMOS processes
- Knowledge of semiconductor devices and fabrication principles including; matching, electromigration, RF delay, parasitic coupling, signal balancing
- Knowledge of nanometer issues such as Well-Proximity Effect (WPE), Shallow Trench Isolation (STI), multiple patterning, and pattern density management
- Must understand issues of IR drop, RC delay, electromigration, self-heating and parasitic capacitance.
- Must recognize failure prone circuits and layout structures, have experience with analog and DFM best practices, and act proactively with circuit designers to apply the best solution to problems.
- Proficiency with industry-standard layout and verification tool; Cadence: Virtuoso IC6.1, Assura, PVS; Mentor: Calibre
- 3+ years experience in a similar role
- Excellent written and verbal communications skills
- Educational: BSEE or BSCS
Job Site: R2 Semiconductor, Inc., 1196 Borregas Avenue, Suite 201, Sunnyvale, CA 94089
Hours: Full-time (40 hours per week)
Contact: Send resume HR, R2 Semiconductor, Inc., 1196 Borregas Avenue, Suite 201, Sunnyvale, CA 94089